High performance capacitor

ABSTRACT

A capacitor includes a controlled collapse chip connection system coupled by vias to a plurality of conductive layers embedded in a dielectric. The capacitor and a die can each be mounted on opposite surfaces of a substrate using a controlled collapse chip connection. The controlled collapse chip connection provides a large number of leads for coupling to the conductive layers of the capacitor. The large number of leads reduce the inductance in the connection. For a thin substrate, the length of the conductive material connecting the capacitor to the die is short, and the inductance and resistance of the conductive material is low. A system comprising two dies can be fabricated in a small volume using a plurality of substrates and a single controlled collapse chip connection compatible capacitor for decoupling the two dies.

[0001] This application is a divisional of application U.S. Ser. No.09/473,315, filed on Dec. 28, 1999.

FIELD

[0002] The present invention relates to capacitors, and moreparticularly to capacitors having a high capacitance, low inductance,and low resistance.

BACKGROUND

[0003] Voltage levels on a die exhibit a droop when there is a suddenincrease in demand for power on the die. This voltage droop on the dieincreases the switching time of the transistors on the die, whichdegrades the performance of the system fabricated on the die. Todecrease the voltage droop during power surges, discrete decouplingcapacitors are mounted adjacent to the die and connected to theconductors that provide power to the die. For a processor die, the dieis mounted on a substrate, and a ring of capacitors, usually ten tofifteen two microfarad capacitors, are mounted on the substrate alongthe periphery of the die. These capacitors are coupled to the powersupply connections at the die through lands formed on the substrate.Problems with this decoupling solution and the capacitors used toimplement this solution are long standing, well known, and interrelated.

[0004] One problem with this decoupling solution is that a large numberof external decoupling capacitors are required to control the voltagedroop on a die. Mounting a large number of external decouplingcapacitors wastes substrate real estate and reduces the die packingdensity on the substrate. In addition, surface area on the substrate isreserved for handling and mounting the discrete capacitors, and thisreserved area is unavailable for mounting other information processingdies.

[0005] A second problem with this decoupling solution relates to thelong leads needed to connect the capacitors to the power supplyconnections sites on the die. Power supply connection sites are usuallyscattered across a die. In general, it is desirable to run short leadsfrom a power supply plane in a substrate to the power supply sites onthe die. Unfortunately, with the decoupling capacitors located near theperiphery of the die, long leads must be run to the power supplyconnection sites scattered across the die. The long leads increase theinductance and resistance of the decoupling capacitors, which tends toincrease the voltage droop in response to a power surge. The long leadsused to connect a die to a decoupling capacitor limit the high frequencyperformance of the decoupling capacitor.

[0006] A third problem is that capacitors having a large capacitancevalue typically have a large inherent inductance and resistance. Thisinherent inductance and resistance causes a large voltage droop at thedie.

[0007] One solution to these problems is to fabricate a large number ofcapacitors on the die for decoupling the power supply connections on thedie. Unfortunately, capacitors already take up a large amount of realestate on a die for a typical integrated circuit, and fabricating morecapacitors on a die reduces the area available for informationprocessing circuits.

[0008] For these and other reasons there is a need for the presentinvention.

SUMMARY

[0009] A capacitor comprises a plurality of conductive layers embeddedin a dielectric. A plurality of vias couple at least two of theplurality of conductive layers to a plurality of connection sites.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1A is an illustration of a cross-sectional side view of someembodiments of a capacitor of the present invention.

[0011]FIG. 1B is an illustration of a top view of a capacitor showingone embodiment of a controlled collapse chip connection pattern.

[0012]FIG. 2 is an illustration of a cross-sectional view of someembodiments of a system including a capacitor coupled to a plurality ofsubstrates.

[0013]FIG. 3 is an illustration of a cross-sectional view of oneembodiment of a system including a die and a capacitor coupled to asubstrate.

[0014]FIG. 4 is an illustration of a cross-sectional view of someembodiments of a system including capacitor coupled to a plurality ofelectronic dies.

[0015]FIG. 5 is an illustration of a cross-sectional view of someembodiments of a system including a capacitor coupled to a dielectricsubstrate and electrically coupled to a die.

DETAILED DESCRIPTION

[0016] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificpreferred embodiments in which the inventions may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be utilized and that logical, mechanical andelectrical changes may be made without departing from the spirit andscope of the present invention. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the claims.

[0017] The present invention provides a high capacitance, low profilecapacitor having a low inductance and a low resistance and a system formounting the capacitor close to a die. To fabricate a high capacitancelow profile capacitor, a plurality of thin screen printed dielectricsheets are stacked to form the capacitor. To reduce the inductance andresistance in the capacitor leads, a large number of vias are coupled tothe conductive layers printed on the stacked dielectric sheets. Finally,to control the length of the leads that couple the capacitor to a die,the vias at the surface of the capacitor are fabricated to couple to asubstrate using controlled collapse chip connection technology.Alternatively, to control the length of the leads that couple thecapacitor to a die, the capacitor is mounted on a laminated layer andvias are laser drilled and plated to provide the electrical connectionto the capacitor.

[0018]FIG. 1A is an illustration of a cross-sectional side view of someembodiments of capacitor 100 of the present invention. Capacitor 100, inone embodiment, is a multilayered capacitor including a first pluralityof conductive layers 103 and 104 interlaced with a second plurality ofconductive layers 105 and 106. Increasing the number of conductivelayers in capacitor 100 increases the capacitance. In one embodiment,capacitor 100 has about 50 conductive layers and a capacitance ofbetween about 20 microfarads and 30 about microfarads. Conductive layers103-106 are fabricated from a conductive material. For example, in oneembodiment, conductive layers 103-106 are fabricated from platinum.Alternatively, conductive layers 103-106 are fabricated from palladium.In still another alternate embodiment, conductive layers 103-106 arefabricated from tungsten. Conductive layers 103-106 are embedded indielectric 113. Conductive layers 103 and 104 are coupled together byvias 115 and 116, and conductive layers 105 and 106 are coupled togetherby vias 117 and 118. In one embodiment, vias 115-118 are plated throughholes that terminate on outer surfaces 127 and 130 in a plurality ofconnection sites, such as controlled collapse chip connection (C4) sites133. A large number of C4 sites decreases the resistance and theinductance of capacitor 100, which improves the performance of capacitor100 as a decoupling capacitor. In one embodiment, capacitor 100 hasabout 4000 C4 sites. Controlled collapse chip connection sites 133 arenot limited to being fabricated on a single surface. In one embodiment,C4 sites 133 are fabricated on outer surfaces 127 and 130. Providing C4sites on a plurality of surfaces increases the number of electronic diesor devices that can be coupled to capacitor 100. Coupling structures forcapacitor 100 are not limited to C4 structures. In one embodiment, vias115-118 terminate on outer surfaces 127 and 130 in pads suitable forcoupling to a substrate, an electronic device, or a die.

[0019] In one embodiment, capacitor 100 has a thickness 136 of betweenabout 0.5 millimeter and about 1 millimeter, a top surface area of about1 cm², and a capacitance of between about 20 microfarads and about 30microfarads. A capacitance of between about 20 microfarads and about 30microfarads makes capacitor 100 suitable for use in decoupling highfrequencies that appear on power supply lines in complex digitalsystems, such as microprocessors. A thickness 136 of between about 0.5millimeter and about 1 millimeter makes capacitor 100 suitable forpackaging with communication devices, such as cell phones, that arepackaged in a small volume.

[0020]FIG. 1B is an illustration of a top view of capacitor 100 of FIG.1A showing one embodiment of a pattern of controlled collapse chipconnection sites. In one embodiment, the controlled collapse connectionsites 133 have a pitch of between about 100 microns and about 500microns. A pitch of between about 100 and about 500 microns reduces theinductance and resistance in the connections. In one embodiment, C4 site139 is coupled to a high voltage level, and C4 sites 142, 145, 148, and151 are coupled to a low voltage level. Each high voltage level C4 siteis surrounded by four low voltage level sites. This pattern of powerdistribution in the C4 sites reduces the inductance and resistance incapacitor 100, which improves the high frequency performance ofcapacitor 100.

[0021] For one embodiment of a method for fabricating capacitor 100, aplurality of dielectric sheets are screen printed with a tungsten pasteor other suitable suspension of tungsten and stacked. The dielectricsheets are fabricated from barium titanate and have a thickness ofbetween about 5 microns and about 7 microns. The tungsten paste formsthe conductive layers 103-106 of capacitor 100. To add strength to thestack, slightly thicker dielectric sheets are used to form the top andbottom layers of the stack. Via holes are formed in the stack to coupleconductive layers 103-106 to controlled collapse chip connection sites133. Processes suitable for use in forming the via holes includemechanical drilling, laser drilling, and etching. The via holes arefilled with a metal slurry, which, in one embodiment, is formed fromtungsten. To further increase the rigidity of the stack, the stack isco-fired at about 1500 degrees centigrade and diced into individualcapacitors.

[0022]FIG. 2 is an illustration of a cross-sectional view of someembodiments of system 200 for coupling capacitor 100 to substrates 206and 209. Substrates 206 and 209, in one embodiment, are fabricated froma ceramic. Alternatively, substrate 206 is a die, such as a silicon die,and substrate 209 is fabricated from a ceramic. In one embodiment,capacitor 100 is coupled to substrates 206 and 209 through controlledcollapse chip connections (C4) 210 and 211. C4 connection sites 133 onthe surfaces 127 and 130 of capacitor 100 are coupled through solderballs 215 to connection sites 218 and substrates 206 and 209. First andsecond metallization layers 221 and 224 in substrate 206 and first andsecond metallization layers 227 and 230 in substrate 209 can be coupledto devices mounted on substrates 206 and 209, thereby coupling capacitor100 to the devices. The capability to couple capacitor 100 to aplurality of substrates permits increased packing densities for complexelectronic devices fabricated in connection with substrates 206 and 209.For example, several microprocessors can be packaged on substrates 206and 209, and the power supply connections for the severalmicroprocessors can be decoupled by capacitor 100. By reducing thenumber of discrete decoupling capacitor packages that are required todecouple the several microprocessors, the reliability of the system 200is increased.

[0023]FIG. 3 is an illustration of a cross-sectional view of oneembodiment of system 300 for coupling die 303 to capacitor 100 throughcommon substrate 306. In one embodiment, die 303 includes an electronicdevice, such as a processor, a communication system, or an applicationspecific integrated circuit. Die 303 is coupled to a first surface ofsubstrate 306 by controlled collapse chip connection (C4) 309. Capacitor100 is coupled to a second surface of substrate 306 by controlledcollapse chip connection 312. Conductive vias 315 in substrate 306couple capacitor 100 to die 303. In one embodiment, substrate 306 isfabricated from a ceramic material. Alternatively, substrate 306 isfabricated from an organic material. Preferably, substrate 306 is thin,which permits a short coupling distance between capacitor 100 and die303. In one embodiment, substrate 306 has a thickness 318 of less thanabout 1 millimeter. A short coupling distance reduces the inductance andresistance in the circuit in which capacitor 100 is connected.

[0024]FIG. 4 is an illustration of a cross-sectional view of someembodiments of system 400 including capacitor 100 coupled to electronicdies 403 and 406. Substrate 409 provides a foundation for mounting die403 and capacitor 100. In addition, substrate 409 couples die 403 tocapacitor 100 through vias 412. Similarly, substrate 415 provides afoundation for mounting die 406 and capacitor 100, and couples die 406to capacitor 100 through vias 422. Connections, such as controlledcollapse chip connections 418421 couple die 403, die 406 and capacitor100 to substrates 409 and 415. For substrate 409 having a thickness 423of less than about 1 millimeter and substrate 415 having a thickness 424of less than about 1 millimeter, the resistance and inductance ofcapacitor 100 and vias 412 and 422 is low. So, decoupling power supplyconnections at die 403 and 406 is improved by packaging dies 403, 406and capacitor 100 as described above.

[0025]FIG. 5 is an illustration of a cross-sectional view of someembodiments of a system 500 including capacitor 503 coupled to substrate506 and electrically coupled by vias 510 and controlled collapse chipconnection 512 to die 515. Capacitor 503 is coupled to power supplyconnections on die 515 to decouple the power supply connections at thedie. Capacitor 503 is protected from the environment by molding 518. Inone embodiment, substrate 506 is formed from a low K dielectric and hasa thickness 521 of between about 0.05 millimeters and about 0.1millimeters. A dielectric thickness of between about 0.05 millimeter and0.1 millimeter allows system 500 to be fabricated with shorter capacitorleads than the capacitor leads in system 400. As described above, asystem having short leads between capacitor 503 and die 515 results in acapacitor having a low inductance and a low resistance, which improvesthe performance of the decoupling circuit.

[0026] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

What is claimed is:
 1. A capacitor comprising: a plurality of conductivelayers embedded in a dielectric; and a plurality of vias coupling atleast two of the plurality of conductive layers to a plurality ofconnection sites.
 2. The capacitor of claim 1, wherein the capacitor hasa thickness of between about 0.5 millimeter and about 1 millimeter. 3.The capacitor of claim 2, wherein the capacitor has a capacitance ofbetween about 20 and about 30 microfarads.
 4. The capacitor of claim 1,wherein the plurality of controlled collapse chip connection sites havea pitch of between about 100 and about 500 microns.
 5. The capacitor ofclaim 1, wherein the plurality of vias are plated through holes.
 6. Acapacitor comprising: a plurality of first conductive layers; aplurality of second conductive layers interlaced with the plurality offirst conductive layers; a number of surfaces having a plurality ofconnection sites operable for coupling the capacitor to a substrateusing a controlled collapse chip connection (C4); and a plurality ofvias coupling the plurality of first conductive layers and the pluralityof second conductive layers to at least two of the plurality ofconnection sites.
 7. The capacitor of claim 6, wherein each of theplurality of first conductive layers is fabricated from a tungstenpaste.
 8. The capacitor of claim 6, wherein the number of surfaces istwo.
 9. A capacitor comprising: a multilayered capacitor having a numberof outer surfaces; and a number of pads located on at least two of thenumber of outer surfaces wherein at least two of the number of pads arecapable of being coupled to a substrate using a solder bump.
 10. Thecapacitor of claim 9, wherein the multilayered capacitor includes anumber of parallel conductive layers and the number of pads are coupledto the number of parallel conductive layers through vias.
 11. Thecapacitor of claim 10, wherein the number of conductive layers isgreater than about
 50. 12. The capacitor of claim 11, wherein the numberof pads is greater than about
 4000. 13. A system comprising: a dieincluding an electronic system; a capacitor located less than about 0.1millimeter from the die and coupled to the die, the capacitor is capableof decoupling a power supply connection at the die without additionalcapacitors located external to the die; and a dielectric layer locatedbetween the capacitor and the die.
 14. The system of claim 13, whereinthe dielectric layer has a thickness of between about 0.05 millimetersand about 0.1 millimeters.
 15. A system comprising: a first die; asecond die; and a capacitor having a first surface having a controlledcollapse chip connection coupled to the first die and a second surfacehaving a controlled collapse chip connection coupled to the second die.16. The system of claim 15, wherein the first die includes a processorand the second die includes a communication system.
 17. A systemcomprising: a substrate having a surface; and a capacitor having aplurality of vias coupled to a plurality of conductive layers in thecapacitor, the capacitor is coupled to the surface at a plurality ofconnection sites.
 18. A system comprising: a substrate having a firstsurface and a second surface; a die coupled to the first surface; and acapacitor having a plurality of vias coupled to a plurality ofconductive layers in the capacitor, the capacitor is coupled to thesecond surface by a controlled collapse chip connection and thecapacitor is electrically coupled to the die through the substrate. 19.The system of claim 18, wherein the die includes a processor.
 20. Thesystem of claim 19, wherein the die has a die surface and the capacitorhas a capacitor surface and the capacitor surface is located less thanabout 0.1 millimeter from the die surface.
 21. A system comprising: aprocessor requiring at least 5 watts of power to be operable; and asingle multilayered single package capacitor coupled to the processorand capable of decoupling a power supply from the processor.
 22. Thesystem of claim 21, wherein the single multilayered single packagecapacitor is capable of being mounted on a substrate by a plurality ofsolder bumps.
 23. The system of claim 22, wherein the singlemultilayered capacitor is capable of being mounted on a substrate usinga controlled collapse chip connection.
 24. A method comprising: forminga stack of a plurality of screen printed dielectric sheets; forming aplurality of via holes in the stack; filling at least two of theplurality of via holes with a metal slurry; and co-firing the stack toform a capacitor.
 25. The method of claim 24, further comprising:coupling the stack to a substrate using a controlled collapse chipconnection.
 26. The method of claim 24, further comprising: coupling adie to the substrate and to the capacitor.
 27. A method comprising:forming a capacitor having a plurality of conductive layers and asurface; and forming a pattern of pads on the surface, at least one padin the pattern of pads is capable of being coupled to at least one ofthe plurality of conductive layers and capable of being coupled to asubstrate using a solder bump attachment.
 28. The method of claim 27,further comprising: coupling the capacitor to a ceramic substrate usinga solder bump attachment.
 29. A method comprising: selecting a substratehaving a controlled collapse chip connection capability; and mounting amultilayered capacitor on the substrate using the controlled collapsechip connection capability.